utc M62364 cmos ic utc unisonic technologies co., ltd. 1 qw-r502-008,a 8-bit 8-ch multiplying d-a converter with buffer amplifiers general description the utc M62364 is a cmos 8-bit, 8-ch d/a converter having a multiplying function and output buffer amplifiers. it has a serial data input and can easily communicate with a microcontroller by the simple three-wiring method (di,clk,ld). the output buffer amplifiers operating in ab-class has both sinking and driving capabilities of 1.0ma or more and can operate in a whole supply range from v dd to gnd. the ic is suitable for a use in automatic adjustment applications in conjunction with a mcu by utilizing the terminal do for a cascading connection. features *three-wiring serial data transmission *doubled precision 8-ch d/a converter employing an r-2r with higher-order segment method *8 buffer amplifiers operating in a whole supply voltage range from v dd to gnd *4-quadrant multiplication application digital to analog conversion for consumer and industrial equipment. gain setting and automatic adjustment of display-monitor and ctv. ssop-24 (209mil) sop-24 pin configuration (top view) 1 12 11 10 9 8 7 6 5 4 3 2 13 14 15 16 17 18 19 20 21 22 23 24 m 6 2 3 6 4 v in1 v in2 v in3 v in4 v in5 v in6 v in7 v in8 v out1 v out2 v out3 v out4 v out5 v out6 v out7 v out8 vdaref reset gnd di clk ld v dd do
utc M62364 cmos ic utc unisonic technologies co., ltd. 2 qw-r502-008,a block diagram 12- bi t sh ift r eg ister d 0d 1d 3 d3 d 4d 5 d6 d 7d 8d 9d 10 d 11 12-bit shift register d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 address decoder 8-bit latch 8-bit latch d-a converter d-a converter + - + - + - 19 7 8 2 1 23 20 24 18 6 17 5 di clk reset v in 1v out 1v in8 v out8 vdaref ld d o v dd gnd
utc M62364 cmos ic utc unisonic technologies co., ltd. 3 qw-r502-008,a explanation of terminals pin no. symbol function 8 17 7 6 20 5 23 22 10 3 2 19 24 21 16 13 12 9 4 1 18 v out1 reset ld clk do di v out2 v out3 v out4 v out5 v out6 v out7 v out8 11 14 15 13 12 9 4 1 20 5 23 18 24 21 16 v dd gnd v in 1 v in 2 v in 3 v in 4 v in 5 v in 6 v in 7 v in 8 vdaref serial data input serial data output shift clock input. input data of di are taken into the 12-bit shift register on a rising edge of the clock a low state enables data loading to the 12-bit shift register. during a rising edge of ld, the data will be loaded to the output register reset 8-bit latches d/a converter output with 8-bit resolution d/a converter input power supply ground d/a converter reference voltage input
utc M62364 cmos ic utc unisonic technologies co., ltd. 4 qw-r502-008,a d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 123456789101112 dat a clk (lsb) d0 d1 d2 d3 d4 d5 d6 d7 (lsb) (msb) :dac data d8 d9 d10 d11 :dac select data d8 d9 d10 d11 dac selection 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 don't care v out 1 selection v out8 selection v out7 selection v out6 selection v out5 selection v out4 selection v out3 selection v out2 selection don't care don't care don't care don't care don't care don't care don't care dac select data *data assignment digital format *12bit serial data
utc M62364 cmos ic utc unisonic technologies co., ltd. 5 qw-r502-008,a d0 d7 d6 d5 d4 d3 d2 d1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 dac output vdaref v in -vdaref)/256 G 1+vdaref v in -vdaref)/256 G255 +vdaref v in -vdaref)/256 G3 +vdaref v in -vdaref)/256 G2 +vdaref timing chart *input data carried out ld signal low besides clk signal positive edge. clk,ld is keep generally high level. r d0 d7 d6 d5 d4 d3 d2 d1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 dac output vdaref (v in -v daref )/256 1+v daref (v in -v daref )/256 255 +v daref (v in -v daref )/256 3 +v daref (v in -v daref )/256 2 +v daref timing chart *input data carried out ld signal low besides clk signal positive edge. clk,ld is keep generally high level. *digital data format r di clk ld vo msb lsb d11 d10 d9 d0
utc M62364 cmos ic utc unisonic technologies co., ltd. 6 qw-r502-008,a absolute maximum rating parameter symbol measurement condition value unit supply voltage v dd -0.3 ~ +7.0 v digital input voltage v ind -0.3 ~ +7.0 v analog input voltage v in -0.3 ~ vdd+0.3 v analog output voltage v out -0.3 ~ vdd+0.3 v d-a reference voltage v daref -0.3 ~ vdd+0.3 v operating temperature t opr -20 ~ +75 c storage temperature t stg -40 ~ +125 c electrical characteristics ana/dig common part v dd =5v 10% v dd v in ,gnd,v daref =0v,ta=-20~85 c unless otherwise noted limit parameter symbol measurement conduction min typ max unit supply voltage v dd 2.7 3.0 3.6 v supply current i dd clk=1mhz,vcc=3v,iao=0 a 3.5 ma digital part v dd =5v 10% v dd v in ,gnd,v daref =0v,ta=-20~85 c unless otherwise noted limit parameter symbol test conduction min typ max unit input leak current i ilk v in =0 ~ v dd -10 10 a digital input ?low? voltage i il 0.2 v dd v digital input ?high? voltage i ih 0.8v dd v do terminal output ?low? voltage v ol iol=2.5ma 0.4 v do terminal output ?high? voltage v oh ioh=-400 a v dd-0.4 v analog part v dd =5v 10% v dd v in ,gnd,v daref =0v,ta=-20~85 c unless otherwise noted limit parameter symbol test conduction min typ max unit input current i in v in =3v,vdaref=0v, *proportional to max. input current condition(v in -vdaref) and digital data of each channels. 0.18 ma d-a reference input current i daref v in =3v,vdaref=0v, *proportional to max. input current condition(v in -vdaref) and digital data of each channels -1.44 ma resolution res 8 bit differential nonlinearity dnl -1 1 lsb nonlinearity nl v dd =2.61v,vdaref=0.050v (10mv/1lsb) without load(i ao = 0) -1.5 1.5 lsb i ao = 100 a 0.1 vcc-0.1 buffer amplifier output voltage range v ao i ao = 500 a 0.2 vcc-0.2 v buffer amplifier output current range i ao upper saturation voltage=0.4v lower saturation voltage=0.4v -1 1 ma
utc M62364 cmos ic utc unisonic technologies co., ltd. 7 qw-r502-008,a limit parameter symbol test conduction min typ max unit utput capacitative load co 0.1 f buffer amplifier output impedance ro 5 ? ac characteristics v dd =5v 10% v dd v in ,gnd,v daref =0v,ta=-20~85 c unless otherwise noted limit parameter symbol test conduction min typ max unit clock ?l? pulse width t ckl 200 ns clock ?h? pulse width t ckh 200 ns clock rise time t cr clock fall time t cf 200 ns data set up time t dch 60 ns data hold time t chd 100 ns ld set up time t chl 200 ns ld hold time t ldc 100 ns ld ?h? pulse duration time t ldh 100 ns data output delay time t do c l=100pf 70 350 ns d-a output setting time t ldd c l 100pf,v ao :0.1 = 2.6v this time until the output becomes the final value of 1/2 lsb 300 s timing chart clk di ld d-a output do output tdo tldd tldh tldc tchl tdch tchd tckl tcr tckh tcf
utc M62364 cmos ic utc unisonic technologies co., ltd. 8 qw-r502-008,a utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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